Method and apparatus to serialize parallel data input values

ABSTRACT

A method includes applying a clock signal having an uneven duty cycle to a control input of at least one selection element of a selection circuit having a tree structure that includes multiple selection elements. The tree structure includes a data input tier and a data output tier.

CLAIM OF PRIORITY

The present application claims priority from and is a divisional ofpending U.S. patent application Ser. No. 12/789,566, filed May 28, 2010,entitled “METHOD AND APPARATUS TO SERIALIZE PARALLEL DATA INPUT VALUES,”the content of which is incorporated by reference herein in itsentirety.

FIELD

The present disclosure is generally related to a method and apparatus toserialize parallel data input values.

DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and more powerfulcomputing devices. For example, there currently exist a variety ofportable personal computing devices, including wireless computingdevices, such as portable wireless telephones, personal digitalassistants (PDAs), and paging devices that are small, lightweight, andeasily carried by users. More specifically, portable wirelesstelephones, such as cellular telephones and Internet Protocol (IP)telephones, can communicate voice and data packets over wirelessnetworks. Many such wireless telephones incorporate additional devicesto provide enhanced functionality for end users. For example, a wirelesstelephone can also include a digital still camera, a digital videocamera, a digital recorder, and an audio file player. Also, suchwireless telephones can process executable instructions, includingsoftware applications, such as a web browser application, that can beused to access the Internet. As such, these wireless telephones caninclude significant computing capabilities.

Portable computing devices may require the conversion of parallel datavalues to serial data values. For example, a display controller in theportable computing device may output parallel data values that need tobe serialized before being sent to the display. In some cases, thenumber of data values provided in parallel is an odd number or an evennumber that is not a power of two. Implementations configured to handlethese cases may suffer from increased complexity in the conversionprocess, bandwidth limitations, high power consumption, and low jitterrequirements.

SUMMARY

A selection circuit is described that may be a low-power high-speedmultiplexer or data serializer using low voltage differential signaling(LVDS). The selection circuit may be implemented using latch-freecombinatorial logic circuits in a tree structure that receive paralleldata input values and provide serial data output values.

The combinatorial logic circuits may be combinatorial gate multiplexers,such as NAND gate multiplexers. The selection circuit may includemultiple tiers in which combinatorial gate multiplexers may serve asselection elements, delay elements, logic operation elements, or anycombination thereof. Multi-phase clock signals may provide controlsignals to the combinatorial logic circuits of the selection circuit.The multi-phase clock signals may each have a different phase, but thesame period. The period of the multi-phase clock signals may beapproximately the same as that of a system clock to reduce powerconsumption. The output tier of the selection circuit may include acombinatorial gate multiplexer as a root selection element to selectbetween data provided from different branches in the tree structure. Themulti-phase clock signals may be applied to different tiers of the treestructure such that the root selection element provides serial outputdata in a particular sequence.

In a particular embodiment, a method of serializing parallel data inputvalues includes receiving multiple data input values in parallel at aninput tier of a selection circuit, where the input tier includesmultiple combinatorial gate multiplexers. The method further includesselecting an output value at an output tier of the selection circuit,where the output tier includes at least one combinatorial gatemultiplexer.

In another particular embodiment, the method includes receiving a firstdata input and a second data input at a combinatorial logic circuit. Themethod further includes receiving a first signal at a first controlinput of the combinatorial logic circuit. The first signal is formed bycombining a first clock signal having a first phase with a second clocksignal having a second phase. The method further includes receiving asecond signal at a second control input of the combinatorial logiccircuit. The second signal is formed by combining a third clock signalhaving a third phase with a fourth clock signal having a fourth phase.The method further includes selecting the first data. input or thesecond data input as a selected output based on the first signal and thesecond signal.

In another particular embodiment, the method includes applying a clocksignal having an uneven duty cycle to a control input of at least oneselection element of a selection circuit. The selection circuit has atree structure that includes multiple selection elements. The treestructure includes a data input tier and a data output tier.

In another particular embodiment, an apparatus includes an input set ofselection elements in an input tier of a tree structure and a selectionelement in an output tier of the tree structure. The input tier includesinputs to receive input data from a parallel interface, and the outputtier includes an output to provide serial output data. At least one ofthe selection elements includes a latch-free circuit that includes NANDlogic circuits.

One particular advantage provided by at least one of the disclosedembodiments is that the high speed data serializer is capable of highspeed, low power, and robust conversion of parallel data input values toserial data output values, where the number of parallel data inputvalues may be an odd number or an even number that is not a power oftwo.

Other aspects, advantages, and features of the present disclosure willbecome apparent after review of the entire application, including thefollowing sections: Brief Description of the Drawings, DetailedDescription, and the Claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a particular illustrative embodiment of anapparatus with a selection circuit having a tree structure that can beused to serialize parallel data input values;

FIG. 2 is a waveform diagram of a particular illustrative embodimentdepicting timing related to operating an apparatus with a selectioncircuit having a tree structure to serialize parallel data input values;

FIG. 3 is a diagram of a second particular illustrative embodiment of anapparatus with a selection circuit having a tree structure that can beused to serialize parallel data input values;

FIG. 4 is a waveform diagram of a second particular illustrativeembodiment depicting timing related to operating an apparatus with aselection circuit having a tree structure to serialize parallel datainput values;

FIG. 5 is a flow chart of a particular illustrative embodiment of amethod of serializing parallel data input values with a selectioncircuit having a tree structure;

FIG. 6 is a flow chart of a second particular illustrative embodiment ofa method of serializing parallel data input values with a selectioncircuit having a tree structure;

FIG. 7 is a block diagram of a portable device including an apparatuswith logic circuits in a tree structure to serialize parallel data inputvalues; and

FIG. 8 is a data flow diagram illustrating a manufacturing process foruse with an apparatus with logic in a tree structure to serializeparallel data input values.

DETAILED DESCRIPTION

A selection circuit is described that may be a low-power high-speedmultiplexer or data serializer implemented using latch-freecombinatorial gate multiplexers in a tree structure. The selectioncircuit receives multiple data input values in parallel at an input tierand selects an output value at an output tier. The input tier mayinclude multiple combinatorial gate multiplexers, and the output tiermay include at least one combinatorial gate multiplexer.

Referring to FIG. 1, a particular illustrative embodiment of anapparatus that is operable to serialize parallel data input values isdisclosed and generally designated 100. The apparatus 100 includes aparallel interface 102 and a selection circuit 101 having multiplecombinatorial logic circuits, such as a representative combinatoriallogic circuit 124 illustrated as including a combinatorial gatemultiplexer. The multiple combinatorial logic circuits may be multiplecombinatorial gate multiplexers and may be distributed to form a treestructure. The apparatus 100 may be configured in a tree structure andmay include a first branch 133 and a second branch 139 of the treestructure. The multiple combinatorial gate multiplexers may be groupedinto multiple tiers, such as an input tier 103, an intermediate tier105, and an output tier 107. The multiple combinatorial gatemultiplexers may serve as selection elements, delay elements, logicoperation elements, or any combination thereof in an illustrativeembodiment, each of the combinatorial gate multiplexers of the apparatus100 has the same internal logic configuration.

The parallel interface 102 may be configured to receive parallel datainput values D0-D6. However, it is to be understood that the parallelinterface 102 may be configured to receive any number of parallel datainput values. The input data values D0-D6 received at the parallelinterface 102 may be provided to the input tier 103 that includesmultiple combinatorial gate multiplexers. The data input value D0 isreceived at an interface input 134, the data input value D1 is receivedat an interface input 136, the data input value D2 is received at aninterface input 138, the data input value D3 is received at an interfaceinput 140, the data input value D4 is received at an interface input142, the data input value D5 is received at an interface input 144, andthe data input value D6 is received at an interface input 146. Theinterface inputs 134, 136, and 138 may provide the data input valuesD0-D2 to the first branch 133 and the interface inputs 140, 142, 144,and 146 may provide the data input values D3-D6 to the second branch139.

The input tier 103 may include an input set of selection elements, suchas combinatorial gate multiplexers 104, 106, 108, and 110, The inputtier 103 includes inputs to receive input data from the parallelinterface 102. The combinatorial gate multiplexer 104 may be configuredto receive the data input value D0 via a data path 148 and to receivethe data input value D1 via a data path 150. The combinatorial gatemultiplexer 106 may be configured to receive the data input value D2 viaa data path 152. The combinatorial gate multiplexer 108 my be configuredto receive the data input value D3 via a data path 154 and to receivethe data input value D4 via a data path 156. The combinatorial gatemultiplexer 110 may be configured to receive the data input value D5 viaa data path 158 and to receive the data input value D0 via a data path160.

The combinatorial gate multiplexers in the input tier 103 also receiveclock signals at control inputs to determine Which data input values arepassed to the next tier. For example, the combinatorial gate multiplexer104 receives a CLK9 clock signal via a data path 180 and a CLK2 clocksignal via a data path 166. The combinatorial gate multiplexer 106receives a CLK13 clock signal via a data path 188 and a CLK6 clocksignal via a data path 174. The combinatorial gate multiplexer 108receives a CLK1 clock signal via a data path 164 and a CLK8 clock signalvia a data path 178. The combinatorial gate multiplexer 110 receives aCLK5 clock signal via a data path 172 and a CLK12 clock signal via adata path 186.

The selected data input value at the combinatorial gate multiplexer 104is passed as an intermediate data value to a combinatorial gatemultiplexer 120 of the intermediate 105 via a data path 149. Theselected data input value at the combinatorial gate multiplexer 106 ispassed as an intermediate data value to the combinatorial gatemultiplexer 120 of the intermediate tier 105 via a data path 153. Theselected data input value at the combinatorial gate multiplexer 108 ispassed as an intermediate data value to a combinatorial gate multiplexer122 of the intermediate tier 105 via a data path 155. The selected datainput value at the combinatorial gate multiplexer 110 is passed as anintermediate data value to the combinatorial gate multiplexer 122 of theintermediate tier 105 via a data path 159.

The intermediate tier 105 may include an intermediate set of selectionelements, such as the combinatorial gate multiplexer 120 and thecombinatorial gate multiplexer 122. The intermediate tier 105 isoperative to select between data received from the input tier 103 and toprovide selected data to the output tier 107. The intermediate tier 105may further include a combinatorial gate multiplexer 112, acombinatorial gate multiplexer 114, a combinatorial gate multiplexer116, and a combinatorial gate multiplexer 118. The combinatorial gatemultiplexers 112, 114, 116, and 118 may be configured to operate asdelay elements. An input 0 and its corresponding control input S0 of thecombinatorial gate multiplexer 112 are tied to a low voltage potential,such as around or a negative supply voltage VSS. An input 1 of thecombinatorial gate multiplexer 112 is tied to a high voltage potential,such as a positive power supply voltage VSS, and its correspondingcontrol input S1 receives a CLK11 clock signal via a data path 184. Theoutput of the combinatorial gate multiplexer 112 is provided to acontrol input S1 of the combinatorial gate multiplexer 120 as a delayedversion of the CLK11 clock signal.

An input 1 and its corresponding control input S1 of the combinatorialgate multiplexer 114 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 0 of the combinatorial gatemultiplexer 114 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S0receives a CLK4 clock signal via a data path 170, The output of thecombinatorial gate multiplexer 114 is provided to a control input S0 ofthe combinatorial gate multiplexer 120 as a delayed version of the CLK4clock signal.

An input 0 and its corresponding control input S0 of the combinatorialgate multiplexer 116 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 1 of the combinatorial gatemultiplexer 116 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S1receives a CLK3 clock signal via a data path 168. The output of thecombinatorial gate multiplexer 116 is provided to a control input S1 ofthe combinatorial gate multiplexer 122 as a delayed version of the CLK3clock signal.

An input 1 and its corresponding control input S1 of the combinatorialgate multiplexer 118 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 0 of the combinatorial gatemultiplexer 118 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S0receives a CLK10 clock signal via a data path 182. The output of thecombinatorial gate multiplexer 118 is provided to a control input S0 ofthe combinatorial gate multiplexer 122 as a delayed version of the CLK10clock signal.

The delayed version of the CLK11 clock signal and the delayed version ofthe CLK4 clock signal are provided to control inputs S1 and S0,respectively, of the combinatorial gate multiplexer 120 determine whichintermediate data value to pass through to the output tier 107 via adata path 161. The delayed version of the CLK3 clock signal and thedelayed version of the CLK10 clock signal provided to control inputs S1and S0, respectively, of the combinatorial gate multiplexer 122determine which intermediate data value to pass through to the outputtier 107 via a data path 167.

The output tier 107 includes an output to provide serial output data.The output tier 107 also includes multiple combinatorial gatemultiplexers, including a combinatorial gate multiplexer 124, acombinatorial gate multiplexer 126, a combinatorial gate multiplexer128, a combinatorial gate multiplexer 130, and a combinatorial gatemultiplexer 132. The combinatorial gate multiplexers 126 and 130 may beconfigured to operate as delay elements and the combinatorial gatemultiplexer 128 may be configured to operate as a selection element. Thecombinatorial gate multiplexers 124 and 132 may be configured to operateas logic operation elements configured to perform a logic operation(e.g., AND and OR logic operations) and may also provide a delay. Thedelay elements, the selection element, the logic operation elements, orany combination thereof, may be configured with the same, or similar,combinatorial logic structure.

An input 0 and its corresponding control input S0 of the combinatorialgate multiplexer 124 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 1 of the combinatorial gatemultiplexer 124 receives a CLK0 clock signal via a data path 162 and itscorresponding control input S1 receives a CLK13 clock signal via thedata path 188. The output of the combinatorial gate multiplexer 124 isprovided to a control input S1 of the combinatorial gate multiplexer 126as a first signal. The first signal is formed by the combination of theCLK0 clock signal and the CLK13 clock signal at the combinatorial gatemultiplexer 124. For example, the combination may include an ANT)operation on the CLK0 clock signal and the CLK13 clock signal.

An input 0 and its corresponding control input S0 of the combinatorialgate multiplexer 126 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 1 of the combinatorial gatemultiplexer 126 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S1receives the first signal via a data path 191. The output of thecombinatorial gate multiplexer 126 is provided to a first control inputS1 of the combinatorial gate multiplexer 128 via a data path 192 as adelayed version of the first signal.

An input 0 of the combinatorial gate multiplexer 132 is tied to a highvoltage potential, such as a positive power supply voltage VDD, and itscorresponding control input S1) receives a CLK6 clock signal via thedata path 174. An input 1 of the combinatorial gate multiplexer 132 istied to a high voltage potential, such as a positive power supplyvoltage VDD, and its corresponding control input S1 receives a CLK7clock signal via a data path 176. The output of the combinatorial gatemultiplexer 132 is provided to a control input S0 of the combinatorialgate multiplexer 130 as a second signal. The second signal is formed bythe combination of the CLK6 clock signal and the CLK7 clock signal atthe combinatorial gate multiplexer 132. For example, the combination mayinclude an OR operation on the CLK6 clock signal and the CLK7 clocksignal.

An input 1 and its corresponding control input S1 of the combinatorialgate multiplexer 130 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 0 of the combinatorial gatemultiplexer 130 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S0receives the second signal via a data path 193. The output of thecombinatorial gate multiplexer 130 is provided to a second control inputS0 of the combinatorial gate multiplexer 128 via a data path 194 as adelayed version of the second signal.

The combinatorial gate multiplexer 128 is a root selection element thatselects between the data values provided by the first branch 133 and thesecond branch 139 based on the delayed first signal at the first controlinput S1 and the delayed second signal at the second control input S0.The intermediate data value provided by the selected branch is passedthrough the root selection element and provided as serial output data ata data path 190.

In an illustrative embodiment, the tree structure of the selectioncircuit 101 is a balanced tree structure. Regardless of the number ofparallel data input values, the tree structure may be configured toinclude the same number of selection elements in each branch where thebranches are both coupled to a root selection element at the output tierfor selecting between the branches. The balanced tree structure mayinclude a root selection element (e.g., combinatorial gate multiplexer128) having a first input from a first selection element, such ascombinatorial gate multiplexer 120, of a first branch 133 of the treestructure and a second input from a second selection element, such ascombinatorial gate multiplexer 122, of a second branch 139 of the treestructure. Also, each branch may include the same number of delayelements and logic operation elements.

In an illustrative embodiment, the combinatorial gate multiplexers maybe latch-free circuits and may include NAND logic circuits. For example,one or more of the multiple combinatorial gate multiplexers may be aNAND multiplexer as illustrated for the combinatorial gate multiplexer124 having three two-input NAND gates, in which a first NAND gate 109has an input 0 and a control input S0 and a second NAND gate 111 has aninput 1 and a control input S1. The output of the first NAND gate 109and the second NAND gate 111 are provided to a third NAND gate 113,whose output is the output of the NAND multiplexer.

During operation, the selection circuit 101 can operate as a multiplexeror a serializer by receiving the multiple data input values in parallelat the input tier 103 of the selection circuit 101 and selecting anoutput value at the output tier 107 of the selection circuit 101 togenerate a serial data output. Each of the multiple combinatorial gatemultiplexers 104-110 in the input tier 103 can operate as a means forselecting first data in a first tier of the tree structure and thecombinatorial gate multiplexer 128 can operate as a means for selectingsecond data (e.g., to provide serial output data) in a second tier ofthe tree structure. The means for selecting the first data and the meansfor selecting the second data may be latch-free circuits and may includeNAND logic circuits.

The selection circuit 101 may be configured to operate as a serializerby providing the multi-phase clock signals to the selection circuit 101in such a way that the appropriate data input value is selected at theserial output. As will be illustrated further in FIG. 2, the controlsignals provided to the root selection element 128 of the output tier107 may have duty cycles that are complementary and match the number ofparallel inputs provided to their respective branches, whereas themulti-phase clock signals CLK0-CLK13 each have a duty cycle of 50%. Forexample, the first branch 133 receives three of the seven parallel datainput values D0-D2. The first output control signal provided at thefirst control input via the data path 192 is a logic level high forthree clock cycles and a logic level low for four clock cycles. When thefirst control signal is a logic level high, the data values, D0-D2, fromthe first branch 133 are provided in order at the serial output as aresult of the selections of the input and intermediate tiers, 103 and105. The second branch 139 receives the remaining four of the sevenparallel data input values D3-D6. The second output control signalprovided at the second control input via the data path 194 is a logiclevel low for three clock cycles and a logic level high for four clockcycles, and is complementary to the first control signal. When thesecond control signal is a logic level high, the data values, D3-D6,from the second branch 139 are provided in order at the serial output asa result of the selections of the input and intermediate tiers, 103 and105.

The selection circuit 101 of FIG. 1 does not suffer from the highcomplexity, bandwidth limitations, high power consumption, and lowjitter requirements that may occur in other implementations. Forexample, a latch implementation may consume more power than theselection circuit 101 because latches can require a clock that is Ntimes faster than the incoming data, where N is the number of parallelinputs. Also, a latch implementation can be bandwidth limiting becauseit requires relatively long setup and hold times and a low-jitter clock.Conventional implementations that do not use latches may only be able toprocess parallel inputs where the number of inputs are powers of two ormay be bandwidth limited and may suffer from high power consumptionbecause of a heavily loaded output. The selection circuit 101 provides alatch-free implementation that reduces circuit complexity by using thesame, or similar, combinational logic circuits throughout the selectioncircuit 101 and is capable of processing an odd number of inputs and aneven number of inputs that is not a power of two. The selection circuit101 may also consume less power and have a higher bandwidth and morefavorable jitter requirements than implementations that use latches orheavily loaded outputs.

Referring to FIG. 2, a waveform diagram is illustrated and generallydesignated 200. The waveform diagram 200 illustrates waveforms that maybe used during operation of apparatus 100. The waveform diagram 200includes waveforms for multi-phase clock signals 262, 264, 266, 268,270, 272, 274, 276, 278, 280, 282, 284, 286, and 288, where themulti-phase clock signal 262 corresponds to the CLK0 clock signal ofFIG. 1, the multi-phase clock signal 264 corresponds to the CLK1 clocksignal, the multi-phase clock signal 266 corresponds to the CLK2 clocksignal, the multi-phase clock signal 268 corresponds to the CLK3 clocksignal, the multi-phase clock signal 270 corresponds to the CLK4 clocksignal, the multi-phase clock signal 272 corresponds to the CLK5 clocksignal, the multi-phase clock signal 274 corresponds to the CLK6 clocksignal, the multi-phase clock signal 276 corresponds to the CLK7 clocksignal, the multi-phase clock signal 278 corresponds to the CLK8 clocksignal, the multi-phase clock signal 280 corresponds to the CLK9 clocksignal, the multi-phase clock signal 282 corresponds to the CLK10 clocksignal, the multi-phase clock signal 284 corresponds to the CLK11 clocksignal, the multi-phase clock signal 286 corresponds to the CLK12 clocksignal, and the multi-phase clock signal 288 corresponds to the CLK13clock signal.

The waveform diagram 200 includes waveforms for output clock signals 292and 294, where the output clock signal 292 corresponds to the firstsignal whose delayed version is provided to the root selection element128 of FIG. 1 via the data path 192 and the output clock signal 294corresponds to the second signal whose delayed version provided to theroot selection element 128 via the data path 194.

The waveform diagram 200 includes parallel input data values 234, 236,238, 240, 242, 244, and 246, received in parallel at the parallelinterface 102 of FIG. 1. The parallel data input value 234 correspondsto data input value D0 received at the interface input 134, the paralleldata input value 236 corresponds to data input value D1 received at theinterface input 136, the parallel data input value 238 corresponds todata input value D2 received at the interface input 138, the paralleldata input value 240 corresponds to data input value D3 received at theinterface input 140, the parallel data input value 242 corresponds todata input value D4 received at the interface input 142, the paralleldata input value 244 corresponds to data input value D5 received at theinterface input 144, and the parallel data input value 246 correspondsto data input value D6 received at the interface input 146.

The waveform diagram 200 also includes serial output data values 290,where the serial output data values correspond to the serial output dataprovided by the root selection element 128 of FIG. 1 at the data path190.

As illustrated in FIG. 2, each of the multi-phase clock signals has aphase that is different from the other multi-phase clock signals. Themulti-phase clock signals may be generated using a phase locked loop(PLL), a delay locked loop (DLL), a clock divider, or by any othermechanism for generating multi-phase clock signals. The PLL may use aring oscillator as a voltage controlled oscillator component. In anillustrative embodiment, each of the multi-phase clock signals has aduty cycle (i.e., a percentage of a signal's period during which thesignal has a logical high value) of approximately fifty percent (50%).Alternatively, the multi-phase clock signals may have an uneven dutycycle. For example, some of the clock signals may have a duty cyclegreater than 50% while others (e.g., their complements) may have a dutycycle less than 50%.

At the input tier 103 of FIG. 1, the multi-phase clock signal 280 (CLK9)is applied at the data path 180 and the multi-phase clock signal 266(CLK2) is applied at the data path 166 of the combinatorial gatemultiplexer 104. The multi-phase clock signals 280 and 266 arecomplementary (e.g., when one of the multi-phase clock signals is highthe other is low). The multi-phase clock signal 288 (CLK13) is appliedat the data path 188 and the multi-phase clock signal 274 (CLK6) isapplied at the data path 174 of the combinatorial gate multiplexer 106,The multi-phase clock signals 288 and 274 are complementary. Themulti-phase clock signal 264 (CLK1) is applied at the data path 164 andthe multi-phase clock signal 278 (CLK8) is applied at the data path 178of the combinatorial gate multiplexer 108. The multi-phase clock signals264 and 278 are complementary. The multi-phase clock signal 272 (CLK5)is applied at the data path 172 and the multi-phase clock signal 286(CLK12) is applied at the data path 186 of the combinatorial gatemultiplexer 110. The multi-phase clock signals 272 and 286 arecomplementary.

At the intermediate tier 105 of FIG. 1, the multi-phase clock signal 284(CLK11) is applied at the data path 184 of the combinatorial gatemultiplexer 112 and the multi-phase clock signal 270 (CLK4) is appliedat the data path 170 of the combinatorial gate multiplexer 114. Themulti-phase clock signals 284 and 270 are complementary. A delayedversion of the multi-phase clock signal 284 is provided from the outputof the combinatorial gate multiplexer 112 to the control input S1 of thecombinatorial gate multiplexer 120. A delayed version of the multi-phaseclock signal 270 is provided from the output of the combinatorial gatemultiplexer 114 to the control input S0 of the combinatorial gatemultiplexer 120.

The multi-phase clock signal 268 (CLK3) is applied at the data path 168of the combinatorial gate multiplexer 116 and the multi-phase clocksignal 282 (CLK10) is applied at the data path 182 of the combinatorialgate multiplexer 118. The multi-phase clock signals 268 and 282 arecomplementary. A delayed version of the multi-phase clock signal 268 isprovided from the output of the combinatorial gate multiplexer 116 tothe control input S1 of the combinatorial gate multiplexer 122. Adelayed version of the multi-phase clock signal 282 is provided from theoutput of the combinatorial gate multiplexer 118 to the control input S0of the combinatorial gate multiplexer 122.

At the output tier 107 of FIG. 1, the multi-phase clock signal 262(CLK0) is applied at the data path 162 and the multi-phase clock signal288 (CLK13) is applied at the data path 188 of the combinatorial gatemultiplexer 124. In an illustrative embodiment, the combinatorial gatemultiplexer 124 provides an AND operation with the multi-phase clocksignals 262 (CLK0) and 288 (CLK13) to generate the first signalcorresponding to an output clock signal 292 to the combinatorial gatemultiplexer 126 via the data path 191. The combinatorial gatemultiplexer 126 may be configured to provide a delayed version of theoutput clock signal 292 as the delayed first signal to the combinatorialgate multiplexer 128 via the data path 192.

The multi-phase clock signal 274 (CLK6) is applied at the data path 174and the multi-phase clock signal 276 (CLK7) is applied at the data path176 of the combinatorial gate multiplexer 132. In an illustrativeembodiment, the combinatorial gate multiplexer 132 provides an ORoperation with the multi-phase clock signals 274 (CLK6) and 276 (CLK7)to generate the second signal corresponding to an output clock signal294 to the combinatorial gate multiplexer 132 via the data path 193. Thecombinatorial gate multiplexer 130 may be configured to provide adelayed version of the output clock signal 294 provided as the delayedsecond signal to the combinatorial gate multiplexer 128 via the datapath 194.

The output clock signal 292 may have a duty cycle that depends on thenumber of parallel data input values, where the number of parallel datainput values may be an odd number or an even number that is not a powerof two. For example, the number of parallel data input values may beseven and the duty cycle of the output clock signal 292 may be threesevenths ( 3/7) or approximately forty-two percent (42%). The outputclock signal 294 may also have a duty cycle that depends on the numberof parallel data input values. Continuing with the previous example, thenumber of parallel data input values may be seven and the duty cycle ofthe output clock sig al 294 may be four sevenths ( 4/7) or approximatelyforty-two percent (58%).

The output clock signals 292 and 294 may be complementary, asillustrated in FIG. 2, and have periods based on the number of paralleldata input values. The output clock signals 292 and 294 enable dataselection at the combinatorial gate multiplexer 128 for an arbitrarynumber of inputs, and may be generated using the same circuitry as therest of the circuits in the selection circuit 101. Utilizing the samecircuitry for the all of the circuits in the selection circuit 101 mayreduce manufacturing costs and improve timing of the data and controlsignals by reducing disparity between delays in the selection circuit101.

In an illustrative embodiment, the parallel data input values D0-D6 maybe provided as serial data output values 290 in the same order, D0-D6,as illustrated in FIG. 2. Alternatively, the order of the serial dataoutput values 290 may be reversed, D6-D0, or provided in a mixedpattern. The order of the serial data output values 290 may becontrolled by the multi-phase output clock signals CLK0-CLK13. Asillustrated in FIG. 2, the selection of the parallel data input valuesD0-D2 from the first branch 133 commences at time t3 when output clocksignal 292 transitions to a logic high (i.e., a voltage corresponding toa logic high value) and ends at time t6 when the output clock signal 292transitions to a logic low (i.e., a voltage corresponding to a logic lowvalue). The data input value D0 is provided as the serial data output atthe data path 190 between times t3-t4 when the multi-phase clock signal280 (CLK9) is a logic high at the combinatorial gate multiplexer 104 ofFIG. 1 and the delayed version of the multi-phase clock signal 284(CLK11) is a logic at the combinatorial gate multiplexer 120.

The data input value D1 is provided at the serial data output betweentimes t4-t5 when the multi-phase clock signal 266 (CLK2) is a logic highat the combinatorial gate multiplexer 104 and the delayed version of themulti-phase clock signal 284 (CLK11) is a logic high at thecombinatorial gate multiplexer 120. The data input value D2 is providedas the serial data output of the data path 190 between times t5-t6 whenthe multi-phase clock signal 288 (CLK13) is a logic high at thecombinatorial gate multiplexer 106 and the delayed version of themulti-phase clock signal 270 (CLK4) is a logic high at the combinatorialgate multiplexer 120. Selection of the parallel data input values D3-D6from the second branch 139 commences at time t6 when the output clocksignal 294 transitions to a logic high and ends at time t10 when theoutput clock signal 294 transitions to a logic low. The data input valueD3 is provided as the serial data output of the data path 190 betweentimes t6-t7 when the multi-phase clock signal 264 (CLK1) is a logic highat the combinatorial gate multiplexer 108 and the delayed version of themulti-phase clock signal 268 (CLK3) is a logic high at the combinatorialgate multiplexer 122. The data input value D4 is provided as the serialdata output of the data path 190 between times 17-t8 when themulti-phase clock signal 278 (CLK8) is a logic high at the combinatorialgate multiplexer 108 and the delayed version of the multi-phase clocksignal 268 (CLK3) is a logic high at the combinatorial gate multiplexer122. The data input value D5 is provided as the serial data output ofthe data path 190 between times t8-t9 when the multi-phase clock signal272 (CLK5) is a logic high at the combinatorial gate multiplexer 110 andthe delayed version of the multi-phase clock signal 282 (CLK10) is alogic high at the combinatorial gate multiplexer 122. The data inputvalue D6 is provided as the serial data output of the data path 190between times t9-t10 when the multi-phase clock signal 286 (CLK12) is alogic high at the combinatorial gate multiplexer 110 and the delayedversion of the multi-phase clock signal 282 (CLK10) is a logic high atthe combinatorial gate multiplexer 122.

The waveforms of FIG. 2 do not illustrate signal delays associated withthe selection circuit 101 of FIG. 1. The combinatorial gate multiplexers104, 106, 108, and 110 each have an associated delay that may beapproximately equal if the same circuit structure is used for eachcombinatorial gate multiplexer 104-110 in the input tier 103. To avoidhaving the multi-phase clock signals 284, 270, 268, and 282, applied tothe intermediate tier 105 arrive at the combinatorial gate multiplexers120 and 122 before the intermediate data values, the combinatorial gatemultiplexers 112, 114, 116, and 118 may operate as delay elements. Thedelays provided by the delay elements (e.g., the combinatorial gatemultiplexers 112-118) in the intermediate tier 105 may be closelymatched to the delays of the input tier 103 by using the same circuitstructure for each combinatorial gate multiplexer 112-122 in theintermediate tier 105 as is used in the input tier 103. Thecombinatorial gate multiplexers 120 and 122 increase the delay to thepropagating data values that are carried over to the output tier 107. Tofurther synchronize transitions in the output tier 107, thecombinatorial gate multiplexers 124, 126, 130, and 132 may operate asdelay elements. The delays provided by the delay elements (e.g., thecombinatorial gate multiplexers 124, 126, 130, 132) in the output tier107 may be closely matched to the delays to the data values caused inthe input and intermediate tiers, 103 and 105, by using the same circuitstructure for each combinatorial gate multiplexer 124-128 in the outputtier 107 as is used in the input tier 103 and the intermediate tier 105.By providing the delay elements for the control signals at theintermediate and output tiers, 105 and 107, the selection circuit 101may provide improved transition synchronization throughout the selectioncircuit 101.

Referring to FIG. 3, a particular illustrative embodiment of anapparatus with a selection circuit having a tree structure that can beused to serialize parallel data input values is depicted and generallydesignated 300. The apparatus 300 includes a parallel interface 102 anda selection circuit 301 having multiple combinatorial gate multiplexers.The multiple combinatorial gate multiplexers may be grouped intomultiple tiers, such as an input tier 303, an intermediate tier 305, andan output tier 307. The multiple combinatorial gate multiplexers mayserve as selection elements, delay elements, logic operation elements,or any combination thereof. The combinatorial gate multiplexers may belatch-free circuits.

In an illustrative embodiment, each of the combinatorial gatemultiplexers of the apparatus 300 has the same internal logicconfiguration. In an illustrative embodiment, one or more of themultiple combinatorial gate multiplexers may be a NAND multiplexerhaving three two-input NAND gates, in which a first NAND gate 109 has aninput 0 and a control input S0 and a second NAND gate 111 has an input 1and a control input S1. Outputs of the first NAND gate 109 and thesecond NAND gate 111 are provided to a third NAND gate 113, whose outputis the output of the NAND multiplexer.

The parallel interface 102 pray be configured to receive parallel datainput values D0-D6 and generate output values as described in FIG. 1.The input tier 303 may include an input set of selection elements, suchas combinatorial gate multiplexers 304, 306, 308, and 310. Thecombinatorial gate multiplexer 304 may be configured to receive the datainput value D0 via a data path 148 and to receive the data input valueD1 via a data path 150. The combinatorial gate multiplexer 306 may beconfigured to receive the data input value D2 via a data path 152. Thecombinatorial gate multiplexer 308 may be configured to receive the datainput value D3 via a data path 154 and to receive the data input valueD4 via a data path 156. The combinatorial gate multiplexer 310 may beconfigured to receive the data input value D5 via a data path 158 and toreceive the data input value D6 via a data path 160.

The combinatorial gate multiplexers in the input tier 303 also receiveclock signals at control inputs to determine which data input values arepassed to the next tier. For example, the combinatorial gate multiplexer304 receives a CLK5 clock signal via a data path 372 and a CLK12 clocksignal via a data path 386. The combinatorial gate multiplexer 306receives a CLK11 clock signal via a data path 384 and a CLK4 clocksignal via a data path 370. The combinatorial gate multiplexer 308receives a CLK1 clock signal via a data path 364 and a CLK8 clock signalvia a data path 378. The combinatorial gate multiplexer 310 receives aCLK3 clock signal via a data path 368 and a CLK10 clock signal via adata path 382.

The selected data input value at the combinatorial gate multiplexer 304is passed as an intermediate data value to a combinatorial gatemultiplexer 320 of the intermediate tier 305 via a data path 349. Theselected data input value at the combinatorial gate multiplexer 306 ispassed as an intermediate data value to the combinatorial gatemultiplexer 320 of the intermediate tier 305 via a data path 353. Theselected data input value at the combinatorial gate multiplexer 308 ispassed as an intermediate data value to a combinatorial gate multiplexer322 of the intermediate tier 305 via a data path 355. The selected datainput value at the combinatorial gate multiplexer 310 is passed as anintermediate data value to the combinatorial gate multiplexer 322 of theintermediate tier 305 via a data path 359.

The intermediate tier 305 includes multiple combinatorial gatemultiplexers, including a combinatorial gate multiplexer 312, acombinatorial gate multiplexer 314, a combinatorial gate multiplexer316, a combinatorial gate multiplexer 318, the combinatorial gatemultiplexer 320, and the combinatorial gate multiplexer 322. Thecombinatorial gate multiplexers 312, 314, 316, and 318 may be configuredto operate as delay elements and the combinatorial gate multiplexers 320and 322 may be configured to operate as selection elements. An input 0and its corresponding control input S0 of the combinatorial gatemultiplexer 312 are tied to a low voltage potential, such as ground or anegative supply voltage VSS. An input 1 of the combinatorial gatemultiplexer 312 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S1receives a CLK6 clock signal via a data path 374. The output of thecombinatorial gate multiplexer 312 is provided to a control input S1 ofthe combinatorial gate multiplexer 320 as a delayed version of the CLK6clock signal.

An input 1 and its corresponding control input S1 of the combinatorialgate multiplexer 314 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 0 of the combinatorial gatemultiplexer 314 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S0receives a CLK13 clock signal via a data path 388. The output of thecombinatorial gate multiplexer 314 is provided to a control input S0 ofthe combinatorial gate multiplexer 320 as a delayed version of the CLK13clock signal.

An input 0 and its corresponding control input S0 of the combinatorialgate multiplexer 316 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 1 of the combinatorial gatemultiplexer 316 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S1receives a CLK2 clock signal via a data path 366. The output of thecombinatorial gate multiplexer 316 is provided to a control input S1 ofthe combinatorial gate multiplexer 322 as a delayed version of the CLK2clock signal.

An input 1 and its corresponding control input S1 of the combinatorialgate multiplexer 318 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 0 of the combinatorial gatemultiplexer 318 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S0receives a CLK9 clock signal via a data path 380. The output of thecombinatorial gate multiplexer 318 is provided to a control input S0 ofthe combinatorial gate multiplexer 322 as a delayed version of the CLK9clock signal.

The delayed version of the CLK6 clock signal and the delayed version ofthe CLK13 clock signal are provided to control inputs S1 and S0,respectively, of the combinatorial gate multiplexer 320 to determinewhich intermediate data value to pass through to the output tier 307 viaa data path 361. The delayed version of the CLK2 clock signal and thedelayed version of the CLK9 clock signal provided to control inputs S1and S0, respectively, of the combinatorial gate multiplexer 322determine which intermediate data value to pass through to the outputtier 307 via a data path 367.

The output tier 307 includes multiple combinatorial gate multiplexers,including a combinatorial gate multiplexer 324, a combinatorial gatemultiplexer 326, a combinatorial gate multiplexer 328, a combinatorialgate multiplexer 330, and a combinatorial gate multiplexer 332. Thecombinatorial gate multiplexers 324, 326, 330, and 332 may be configuredto operate as delay elements and the combinatorial gate multiplexer 328may be configured to operate as a selection element.

An input 0 and its corresponding control input S0 of the combinatorialgate multiplexer 324 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 1 of the combinatorial gatemultiplexer 324 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S1receives the CLK0 clock signal via the data path 362, The output of thecombinatorial gate multiplexer 324 is provided to a control input S1 ofthe combinatorial gate multiplexer 326 as a first signal. The firstsignal is a delayed version of the CLK0 clock signal.

An input 0 and its corresponding control input S0 of the combinatorialgate multiplexer 326 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 1 of the combinatorial gatemultiplexer 326 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S1receives the first signal via a data path 391. The output of thecombinatorial gate multiplexer 326 is provided to a first control inputS1 of the combinatorial gate multiplexer 328 via a data path 392 as adelayed version of the first signal.

An input 0 of the combinatorial gate multiplexer 332 is tied to a highvoltage potential, such as a positive power supply voltage VDD, and itscorresponding control input S0 receives the CLK7 clock signal via thedata path 376. An input 1 and its corresponding control input S1 of thecombinatorial gate multiplexer 324 are tied to a low voltage potential,such as ground or a negative supply voltage VSS. The output of thecombinatorial gate multiplexer 332 is provided to a control input S0 ofthe combinatorial gate multiplexer 330 as a second signal. The secondsignal is a delayed version of the CLK7 clock signal.

An input 1 and its corresponding control input S1 of the combinatorialgate multiplexer 330 are tied to a low voltage potential, such as groundor a negative supply voltage VSS. An input 0 of the combinatorial gatemultiplexer 330 is tied to a high voltage potential, such as a positivepower supply voltage VDD, and its corresponding control input S0receives the second signal via a data path 393. The output of thecombinatorial gate multiplexer 330 is provided to a second control inputS0 of the combinatorial gate multiplexer 328 via a data path 394 as adelayed version of the second signal.

The combinatorial gate multiplexer 328 is a root selection element thatselects between the data values provided by a first branch 333 and asecond branch 339 of a tree structure based on the delayed first signalat the first control input S1 and the delayed second signal at thesecond control input S0. The intermediate data value provided by theselected branch is passed through the root selection element andprovided as serial output data at a data path 390.

The selection circuit 301 may be configured to operate as a serializerby providing multi-phase clock signals to the selection circuit 301 insuch a way that the appropriate data input value is selected at theserial output. A clock signal having an uneven duty cycle may be appliedto a control input of at least one selection element of the selectioncircuit 301, such as the combinatorial gate multiplexer 328. As will beillustrated further in FIG. 4, the control signals provided to the rootselection element 328 of the output tier 307 may have duty cycles thatare complementary and match the number of parallel inputs provided totheir respective branches. For example, the first branch 333 receivesthree of the seven parallel data input values D0-D2. The first outputcontrol signal provided at the first control input via the data path 392is a logic level high for three clock cycles and a logic level low forfour clock cycles. When the first control signal is a logic level high,the data values, D0-D2, from the first branch 333 are provided in orderat the serial output as a result of the selections of the input andintermediate tiers, 303 and 305. The second branch 339 receives theremaining four of the seven parallel data input values D3-D6. The secondoutput control signal provided at the second control input via the datapath 394 is a logic level low for three clock cycles and a logic levelhigh for four clock cycles, and is complementary to the first controlsignal. When the second control signal is a logic level high, the datavalues, D3-D6, from the second branch 339 are provided in order at theserial output as a result of the selections of the input andintermediate tiers, 303 and 305.

The selection circuit 301 of FIG. 3 does not suffer from the highcomplexity, bandwidth limitations, high power consumption, and lowjitter requirements that may occur in other implementations. Forexample, a latch implementation may consume more power than theselection circuit 301 because latches can require a clock that is Ntimes faster than the incoming data, where N is the number of parallelinputs. Also, a latch implementation can be bandwidth limiting becauseit requires relatively long setup and hold times and a low-jitter clock.Conventional implementations that do not use latches may only be able toprocess parallel inputs where the number of inputs are powers of two ormay be bandwidth limited and may suffer from high power consumptionbecause of a heavily loaded output. The selection circuit 301 provides alatch-free implementation that reduces circuit complexity by using thesame, or similar, combinational logic circuits throughout the selectioncircuit 301 and is capable of processing an odd number of inputs and aneven number of inputs that is not a power of two. The selection circuit301 may also consume less power and have a higher bandwidth and morefavorable jitter requirements than implementations that use latches orheavily loaded outputs.

Referring to FIG. 4, a waveform diagram is illustrated and generallydesignated 400. The waveform diagram 400 illustrates an operation of theapparatus 300 of FIG. 3. The waveform diagram 400 includes waveforms formulti-phase clock signals 462, 464, 466, 468, 470, 472, 474, 476, 478,480, 482, 484, 486, and 488, where the multi-phase clock signal 462corresponds to the CLK0 clock signal of FIG. 3, the multi-phase clocksignal 464 corresponds to the CLK1 clock signal, the multi-phase clocksignal 466 corresponds to the CLK2 clock signal, the multi-phase clocksignal 468 corresponds to the CLK3 clock signal, the multi-phase clocksignal 470 corresponds to the CLK4 clock signal, the multi-phase clocksignal 172 corresponds to the CLK5 clock signal, the multi-phase clocksignal 474 corresponds to the CLK6 clock signal, the multi-phase clocksignal 476 corresponds to the CLK7 clock signal, the multi-phase clocksignal 478 corresponds to the CLK8 clock signal, the multi-phase clocksignal 480 corresponds to the CLK9 clock signal, the multi-phase clocksignal 482 corresponds to the CLK10 clock signal, the multi-phase clocksignal 484 corresponds to the CLK11 clock signal, the multi-phase clocksignal 486 corresponds to the CLK12 clock signal, and the multi-phaseclock signal 188 corresponds to the CLK13 clock signal.

The waveform diagram 400 also includes serial output data values 490,where the serial output data values correspond to the serial output dataprovided by the root selection element 328 of FIG. 3 at the data path390.

As illustrated in FIG. 4, each of the multi-phase clock signals has aphase different from the other multi-phase clock signals. Themulti-phase clock signals may be generated using a delay locked loop(DLL), a clock divider, or by any other mechanism for generatingmulti-phase clock signals that may have a duty cycle other than 50%. Inan illustrative embodiment, each of the multi-phase clock signals has aduty cycle either less than or greater than fifty percent (50%). Forexample, one of the clock signals may have a duty cycle greater than 50%while its complement may have a duty cycle less than 50%. As illustratedfor 7 inputs, each multi-phase clock signal has a period of seven timeintervals (e.g., from time t0 to time t7), having a first value (e.g.,logic low) for four time intervals and the other value (e.g., logichigh) for three time intervals.

At the input tier 303 of FIG. 3, the multi-phase clock signal 472 (CLK5)is applied at the data path 372 and the multi-phase clock signal 486(CLK12) is applied at the data path 386 of the combinatorial gatemultiplexer 304. The multi-phase clock signals 472 and 486 arecomplementary (e.g., when one of the multi-phase clock signals is highthe other is low). The multi-phase clock signal 484 (CLK11) is appliedat the data path 384 and the multi-phase clock signal 470 (CLK4) isapplied at the data path 370 of the combinatorial gate multiplexer 306.The multi-phase clock signals 484 and 470 are complementary. Themulti-phase clock signal 464 (CLK1) is applied at the data path 364 andthe multi-phase clock signal 478 (CLK8) is applied at the data path 378of the combinatorial gate multiplexer 308. The multi-phase clock signals464 and 478 are complementary. The multi-phase clock signal 468 (CLK3)is applied at the data path 368 and the multi-phase clock signal 482(CLK10) is applied at the data path 382 of the combinatorial gatemultiplexer 310. The multi-phase clock signals 468 and 482 arecomplementary.

At the intermediate tier 305 of FIG. 3, the multi-phase clock signal 474(CLK6) is applied at the data path 374 of the combinatorial gatemultiplexer 312 and the multi-phase clock signal 488 (CLK13) is appliedat the data path 388 of the combinatorial gate multiplexer 314. Themulti-phase clock signals 474 and 488 are complementary. A delayedversion of the multi-phase clock signal 474 is provided from the outputof the combinatorial gate multiplexer 312 to the control input S1 of thecombinatorial gate multiplexer 320. A delayed version of the multi-phaseclock signal 488 is provided from the output of the combinatorial gatemultiplexer 314 to the control input S0 of the combinatorial gatemultiplexer 320.

The multi-phase clock signal 466 (CLK2) is applied at the data path 366of the combinatorial gate multiplexer 316 and the multi-phase clocksignal 480 (CLK9) is applied at the data path 380 of the combinatorialgate multiplexer 318. The multi-phase clock signals 466 and 480 arecomplementary. A delayed version of the multi-phase clock signal 466 isprovided from the output of the combinatorial gate multiplexer 316 tothe control input S1 of the combinatorial gate multiplexer 322. Adelayed version of the multi-phase clock signal 480 is provided from theoutput of the combinatorial gate multiplexer 318 to the control input S0of the combinatorial gate multiplexer 322.

At the output tier 307 of FIG. 3, the multi-phase clock signal 462(CLK0) is applied at the data path 362 of the combinatorial gatemultiplexer 324. The combinatorial gate multiplexer 324 provides adelayed version of the multi-phase clock signal 462 (CLK0) as a firstsignal to the combinatorial gate multiplexer 326 via the data path 391.The combinatorial gate multiplexer 326 may be configured to provide adelayed version of the first signal as the first control signal to thecombinatorial gate multiplexer 328 via the data path 392. Themulti-phase clock signal 462 (CLK0) may have a duty cycle that dependson the number of parallel data input values (e.g., D0-D6), where thenumber of parallel data input values may be a power of two oralternatively may be an odd number or an even number that is not a powerof two. For example, the number of parallel data input values may beseven and the duty cycle of the multi-phase clock signal 462 (CLK0) maybe three sevenths ( 3/7) or approximately forty-two percent (42%).

The multi-phase clock signal 476 (CLK7) is applied at the data path 376of the combinatorial gate multiplexer 332. The combinatorial gatemultiplexer 332 may be configured to provide a delayed version of themulti-phase clock signal 476 (CLK7) as a second signal to thecombinational gate multiplexer 330 via the data path 393. Thecombinatorial gate multiplexer 330 may be configured to provide adelayed version of the second signal as the second control signal to thecombinatorial gate multiplexer 328 via the data path 394. Themulti-phase clock signal 476 (CLK7) may also have a duty cycle thatdepends on the number of parallel data input values. For example, thenumber of parallel data input values may be seven and the duty cycle ofthe multi-phase clock signal 476 (CLK7) may be four sevenths ( 4/7) orapproximately forty-two percent (58%). The multi-phase clock signals 462(CLK0) and 476 (CLK7) may be complementary as illustrated in FIG. 4. Inan illustrative embodiment, the clock signals 462, 464, 466, 468, 470,472, and 474 may have duty cycles less than 50% (e.g., the duty cyclesmay be three sevenths ( 3/7) or approximately forty-two percent (42%))and their complements, the clock signals 476, 478, 480, 482, 484, 486,and 488, may have duty cycles greater than 50% (e.g., the duty cyclesmay be four sevenths ( 4/7) or approximately fifty-eight percent (58%)).

In an illustrative embodiment, the parallel data input values D0-D6 maybe provided as serial data output values 490 in the same order, D0-D6,as illustrated in FIG. 4. Alternatively, the order of the serial dataoutput values 490 may be reversed, D6-D0, or provided in a mixedpattern. The order of the serial data output values 490 may becontrolled by the multi-phase output clock signals CLK0-CLK13. Asillustrated in FIG. 4, selection of the parallel data input values D0-D2from the first branch 333 commences at time t3 when the multi-phaseclock signal 462 (CLK0) transitions to a logic high and ends at time t6when the multi-phase clock signal 462 (CLK0) transitions to a logic low.The data input value D0 is provided as the serial data output at thedata. path 390 between times t3-t4 when the multi-phase clock signal 472(CLK5) is a logic high at the combinatorial gate multiplexer 304 of FIG.3 and the delayed version of the multi-phase clock signal 474 (CLK6) isa logic high at the combinatorial gate multiplexer 320. The data inputvalue D1 is provided as the serial data output at the data path 390between times t4-t5 when the multi-phase clock signal 486 (CLK12) is alogic high at the combinatorial gate multiplexer 304 and the delayedversion of the multi-phase clock signal 274 (CLK3) is a logic high atthe combinatorial gate multiplexer 320. The data input value D2 isprovided as the serial data output at the data path 390 between timest5-t6 when the multi-phase clock signal 484 (CLK11) is a logic high atthe combinatorial gate multiplexer 306 and the delayed version of themulti-phase clock signal 488 (CLK13) is a logic high at thecombinatorial gate multiplexer 320.

Selection of the parallel data input values D3-D6 from the second branch339 commences at time t6 when the multi-phase clock signal 476 (CLK7)transitions to a logic high and ends at time t10 when the multi-phaseclock signal 476 (CLK7) transitions to a logic low. The data input valueD3 is provided as the serial data output between times t6-t7 when themulti-phase clock signal 464 (CLK1) is a logic high at the combinatorialgate multiplexer 308 and the delayed version of the multi-phase clocksignal 466 (CLK2) is a logic high at the combinatorial gate multiplexer322. The data input value D4 is provided as the serial data output atthe data path 390 between times t7-t8 when the multi-phase clock signal478 (CLK8) is a logic high at the combinatorial gate multiplexer 308 andthe delayed version of the multi-phase clock signal 466 (CLK2) is alogic high at the combinatorial gate multiplexer 322. The data inputvalue D5 is provided as the serial data output at the data path 390between times t8-t9 when the multi-phase clock signal 468 (CLK3) is alogic high at the combinatorial gate multiplexer 310 and the delayedversion of the multi-phase clock signal 480 (CLK9) is a logic high atthe combinatorial gate multiplexer 322. The data input value D6 isprovided as the serial data output at the data path 390 between timest9-t10 when the multi-phase clock signal 482 (CLK10) is a logic high atthe combinatorial gate multiplexer 310 and the delayed version of themulti-phase clock signal 480 (CLK9) is a logic high at the combinatorialgate multiplexer 322.

The multi-phase clock signals 462-488 illustrated in FIG. 4 are providedwith an uneven duty cycle whereas the multi-phase clock signals 262-288illustrated in the FIG. 2 have a balanced duty cycle (e.g., a 50% dutycycle). Even though the multi-phase clock signals of FIGS. 2 and 4 havethe same period, the multi-phase clock signals 462-488 of FIG. 4 willhave transitions between logic levels at different times than thecorresponding multi-phase clock signals 262-288 of FIG. 2. As a result,the application of the multi-phase clock signals 262-288 of FIG. 2 tothe apparatus 100 of FIG. 1 may be applicable to a system using a PLL togenerate multi-phase data signals, while application of the multi-phaseclock signals 462-488 of FIG. 4 to the apparatus 300 of FIG. 3 may beapplicable to a system using a DLL or clock divider to generatemulti-phase clock signals.

Referring to FIG. 5, a particular embodiment of a method 500 isillustrated. The method 500 may include receiving multiple data inputvalues in parallel at an input tier of a selection circuit, where theinput tier includes multiple combinatorial gate multiplexers, at 502.For example, apparatus 100 of FIG. 1 includes the selection circuit 101configured to receive data input values D0-D7 from the parallelinterface 102. The parallel interface 102 may be configured to providethe data input values D0-D7 to the combinatorial gate multiplexers 104,106, 108, and 110 of the input tier 103. One or more of thecombinatorial gate multiplexers 104, 106, 108, and 110 may be a NANDmultiplexer, such as the NAND multiplexer illustrated FIG. 1.

The method 500 may further include receiving clock signals, each clocksignal having a different phase, where each NAND multiplexer of theinput tier performs a NAND operation of a particular one of the clocksignals with one of the multiple data input values, at 504. For example,the combinatorial gate multiplexers 104, 106, 108, and 110 of the inputtier 103 of FIG. 1 each receive two multi-phase clock signals where eachof the multi-phase clock signals received at the input tier 103 has adifferent phase. The NAND multiplexers of the input tier 103 may performa NAND operation of the received multi-phase clock signals and datainput values. For example, in an embodiment where the combinatorial gatemultiplexer 104 is a NAND multiplexer, the NAND gate 111 performs a NANDoperation with tire data input value D0 and the CLK9 clock signal, andthe NAND gate 109 performs a NAND operation with the data input value D1and the CLK2 clock signal. The NAND gate 113 performs a NAND operationwith the results from the NAND gate 111 and the NAND gate 109. Theoutput of the NAND gate 113 is provided to a next tier.

The method 500 may further include receiving multiple intermediate datavalues at an intermediate tier of the selection circuit from the inputtier, where the intermediate tier includes multiple combinatorial gatemultiplexers, at 506. For example, the outputs of the combinatorial gatemultiplexers 104, 106, 108, and 110 of FIG. 1 may be provided asintermediate values to the intermediate tier 105. The intermediate tier105 may include the combinatorial gate multiplexers 112, 114, 116, 118,120, and 122.

The method 500 may further include generating an output clock signal foroutput tier based on a combination of the clock signals, at 508. Forexample, the combinatorial gate multiplexer 124 of FIG. 1 may be a NANDmultiplexer and may be configured to perform an AND operation with theCLK0 clock signal and the CLK13 clock signal. The combinatorial gatemultiplexer 124 may be configured to receive the CLK0 clock signal at aninput 1 via the data path 162 and to receive a CLK13 clock signal at acontrol input S1 via the data path 188, where an input 0 and itscorresponding control input S0 are tied to a low logic level. The NANDgate 111 performs a NAND operation with the CLK0 clock signal and theCLK13 clock signal and provides the resulting output as an input to theNAND gate 113. The NAND gate 109 performs a NAND operation with two lowlogic level values and outputs a logic level high value to the NAND gate113. The NAND gate 113 performs a NAND operation with the results fromthe NAND gate 111 and the logic level high value from the NAND gate 109.The first signal provided at the output of the NAND gate 113 isequivalent to an AND operation performed on the CLK0 clock signal andthe CLK13 clock signal.

As another example, the combinatorial gate multiplexer 132 of FIG. 1 maybe a NAND multiplexer and may be configured to perform an OR operationwith the CLK6 clock signal and the CLK7 clock signal. The combinatorialgate multiplexer 132 may be configured to receive the CLK6 clock signalat a control input S0 via the data path 174 and a corresponding input 0may be tied to a high logic level, such as a positive power supplyvoltage VDD. The NAND gate 109 performs a NAND operation with the CLK6clock signal and the high logic level value and provides the resultingoutput as an input to the NAND gate 113. The combinatorial gatemultiplexer 132 may be configured to receive the CLK7 clock signal at acontrol input S1 via the data path 176 and a corresponding input I maybe tied to a high logic level. The NAND gate 111 performs a NANDoperation with the CLK7 clock signal and the high logic level value andprovides the resulting output as an input to the NAND gate 113. The NANDgate 113 performs a NAND operation with the results from the NAND gate111 and the NAND gate 109. The second signal provided at the output ofthe NAND gate 113 is equivalent to an OR operation performed on the CLK6clock signal and with the CLK7 clock signal.

The method 500 may further include applying a delay to a clock signalusing a combinatorial gate multiplexer in the output tier that has asame structure as the root selection element of the output tier, at 510.For example, the combinatorial gate multiplexer 126 of FIG. 1 may beused to delay the first signal received via the data path 191 and toprovide a delayed version of the first signal to the first control inputof the combinatorial gate multiplexer 128. The combinatorial gatemultiplexers 126 and 130 may introduce delays that substantially matchdelays introduced by the combinatorial gate multiplexers 120 and 122.Also, the combinatorial gate multiplexer 130 may be used to delay thesecond signal received via the data path 193 and to provide a delayedversion of the second signal at the second control input of thecombinatorial gate multiplexer 128. The combinatorial gate multiplexers126 and 130 may have the same structure as the combinatorial gatemultiplexer 128 and as the combinatorial gate multiplexers 120 and 122.For example, the combinatorial gate multiplexers 126, 128, and 130 mayeach be NAND multiplexers illustrated in FIG. 1. Further, combinatorialgate multiplexers 124 and 132 may have the same structure as thecombinatorial gate multiplexer 128. Further still, each of thecombinatorial gate multiplexers of the apparatus 100 may have the samestructure as the combinatorial gate multiplexer 128.

The method 500 may further include selecting an output value at anoutput tier of the selection circuit, where the output tier includes atleast one combinatorial gate multiplexer, at 512. For example, thecombinational gate multiplexer 128 of FIG. 1 may be a root selectionelement configured to select an output value from the intermediate datavalues provided by the first branch 133 and the second branch 139.

The method 500 enables conversion of parallel data input values toserial output values in a fast and efficient manner. The method 500 maybe used for any number of multiple parallel data inputs, includingembodiments where the number of parallel data input values is an oddnumber, an even number that is not a power of two, an even number thanis a power of two, or any combination thereof.

Referring to FIG. 6, a particular embodiment of a method 600 isillustrated. The method 600 may include receiving data inputs from aparallel interface, at 602. For example, the selection circuit 101 ofFIG. 1 receives D0-D7 at the input tier 103 from the parallel interface102.

The method 600 may further include receiving a first data input at acombinatorial logic circuit, at 604, and receiving a second data inputat the combinatorial logic circuit, at 606. For example, thecombinatorial gate multiplexer 128 of FIG. 1 may be configured toreceive an intermediate data value passed through the combinatorial gatemultiplexer 120 via the data path 161 as the first data input. Thecombinatorial gate multiplexer 128 may be configured to receive anotherintermediate data value passed through the combinatorial gatemultiplexer 122 via the data path 167 as the second data input.

The method 600 may further include receiving a first signal at a firstcontrol input of the combinatorial logic circuit, the first signalformed by combining a first clock signal having a first phase with asecond clock signal having a second phase, at 608. For example, thecombinatorial gate multiplexer 128 of FIG. 1 may be configured toreceive the delayed version of the first signal at the first controlinput from the combinatorial gate multiplexer 126 via the data path 192.The first signal may be formed at the combinatorial gate multiplexer 124by combining the CLK0 clock signal at the data path 162 and the CLK13clock signal at the data path 188. As illustrated in FIG. 2 themulti-phase clock signals 262 (CLK0) and 288 (CLK13) have differentphases. The combination of the multi-phase clock signals 262 (CLK0) and288 (CLK13) may result in the output clock signal 292 provided to thecombinatorial gate multiplexer 126 via the data path 191 and to thecombinatorial gate multiplexer 128 via the data path 192.

The method 600 may further include receiving a second signal at a secondcontrol input of the combinatorial logic circuit, the second signalformed by combining a third clock signal having a third phase with afourth clock signal having a fourth phase, at 610. For example, thecombinatorial gate multiplexer 128 of FIG. 1 may be configured toreceive the delayed version of the second signal at the second controlinput from the combinatorial gate multiplexer 130 via the data path 194.The second signal may be formed by combining the CLK6 clock signal atthe data path 174 and the CLK7 clock signal at the data path 176 of thecombinatorial multiplexer 132. As illustrated in FIG. 2, the multi-phaseclock signals 274 (CLK6) and 276 (CLK7) have different phases. Thecombination of the multi-phase clock signals 274 (CLK6) and 276 (CLK7)may result in the output clock signal 294 provided to the combinatorialgate multiplexer 130 via the data path 193 and to the combinatorial gatemultiplexer 128.

The method 600 may further include selecting one of the first data inputand the second data input as a selected output based on the first signaland the second signal, where the selected output provides serial data,at 612. For example, the combinatorial gate multiplexer 128 of FIG. 1may be a root selection element configured to select between theintermediate data values provided by the first branch 133 via the datapath 161 and the second branch 139 via the data path 167, where theselection is based on the delayed version of the first signal receivedvia the data path 192 and the delayed version of the second signalreceived via the data path 194.

Referring to FIG. 7, a block diagram of a particular illustrativeembodiment of an electronic device is depicted and generally designated700, The device 700 includes a processor, such as a digital signalprocessor (DSP) 710, coupled to a memory 732, and a serializer usingcombinatorial logic circuits in a tree structure 764. In an illustrativeexample, the serializer using combinatorial logic circuits in a treestructure 764 includes the multiple combinatorial gate multiplexersdepicted in FIG. 1. To illustrate, the serializer using thecombinatorial logic circuits in a tree structure 764 may include theapparatus 100 of FIG. 1 or the apparatus 300 of FIG. 3, may operateaccording to one or more of the methods of FIGS. 5 and 6, or anycombination thereof.

FIG. 7 also shows a display controller 726 that is coupled to thedigital signal processor 710 and to the serializer using combinatoriallogic circuits in a tree structure 764. The display controller 726provides parallel data input values to the serializer usingcombinatorial logic circuits in a tree structure 764 and the serializerusing combinatorial logic circuits in a tree structure 764 converts theparallel data input values into serial data output values and providesthe serial data output values to a display 728. A coder/decoder (CODEC)734 can also be coupled to the digital signal processor 710. A speaker736 and a microphone 738 can be coupled to the CODEC 734.

FIG. 7 also indicates that a wireless controller 740 can be coupled tothe digital signal processor 710 and to a wireless antenna 742. In aparticular embodiment, the DSP 710, the display controller 726, thememory 732, the CODEC 734, the wireless controller 740, and theserializer using combinatorial logic circuits in a tree structure 764are included in a system-in-package or system-on-chip device 722. In aparticular embodiment, an input device 730 and a power supply 744 arecoupled to the system-on-chip device 722. Moreover, in a particularembodiment, as illustrated in FIG. 7, the display 728, the input device730, the speaker 736, the microphone 738, the wireless antenna 742, andthe power supply 744 are external to the system-on-chip device 722.However, each of the display 728, the input device 730, the speaker 736,the microphone 738, the wireless antenna 742, and the power supply 744can be coupled to a component of the system-on-chip device 722, such asan interface or a controller.

FIG. 8 is a data flow diagram of a particular illustrative embodiment ofa manufacturing process to manufacture electronic devices that include aserializer using combinatorial logic in a tree structure.

The foregoing disclosed devices and functionalities may be designed andconfigured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored oncomputer readable media. Some or all such files may be provided tofabrication handlers who fabricate devices based on such files.Resulting products include semiconductor wafers that are then cut intosemiconductor die and packaged into a semiconductor chip. The chips arethen employed in devices described above. FIG. 8 depicts a particularillustrative embodiment of an electronic device manufacturing process800.

Physical device information 802 is received in the manufacturing process800, such as at a research computer 806. The physical device information802 may include design information representing at least one physicalproperty of a semiconductor device, such as the apparatus 100 of FIG. 1,the apparatus 300 of FIG. 3, or any combination thereof. To illustrate,the physical device information 802 may include informationcorresponding the multiple combinatorial gate multiplexers of FIG. 1 or3 in a tree structure. For example, the physical device information 802may include physical parameters, material characteristics, and structureinformation that is entered via a user interface 804 coupled to theresearch computer 806. The research computer 806 includes a processor808, such as one or more processing cores, coupled to a computerreadable medium such as a memory 810. The memory 810 may store computerreadable instructions that are executable to cause the processor 808 totransform the physical device information 802 to comply with a fileformat and to generate a library file 812.

In a particular embodiment, the library file 812 includes at least onedata file including transformed design information. For example, thelibrary file 812 may include a library of semiconductor devicesincluding the apparatus 100 of FIG. 1, the apparatus 300 of FIG. 3, orany combination thereof, that is provided for use w electronic designautomation (FDA) tool 820. To illustrate, the library file 812 mayinclude information corresponding to the multiple combinatorial gatemultiplexers of FIG. 1 or 3 in a tree structure.

The library file 812 may be used in conjunction with the FDA tool 820 ata design computer 814 including a processor 816, such as one or moreprocessing cores, coupled to a memory 818. The FDA tool 820 may bestored as processor executable instructions at the memory 818 to enablea user of the design computer 814 to design a circuit using theapparatus 100 of FIG. 1, the apparatus 300 of FIG. 3, or any combinationthereof, of the library file 812. For example, a user of the designcomputer 814 may enter circuit design information 822 via a userinterface 824 coupled to the design computer 814. The circuit designinformation 822 may include design information representing at least onephysical property of a semiconductor device, such as the apparatus 100of FIG. 1, the apparatus 300 of FIG. 3, or any combination thereof. Toillustrate, the circuit design information may include identification ofparticular circuits and relationships to other elements in a circuitdesign, positioning information, feature size information,interconnection information, or other information representing aphysical property of a semiconductor device.

The design computer 814 may be configured to transform the designinformation, including the circuit design information 822 to comply witha file format. To illustrate, file formation may include a databasebinary file format representing planar geometric shapes, text labels,and other information about a circuit layout in a hierarchical format,such as a Graphic Data System (GDSII) file format. The design computer814 may be configured to generate a data file including the transformeddesign information, such as a GDSII file 826 that includes informationdescribing the apparatus 100 of FIG. 1, the apparatus 300 of FIG. 3, orany combination thereof, in addition to other circuits or information.To illustrate, the GDSII file 826 may include information correspondingthe multiple combinatorial gate multiplexers of FIG. 1 or 3 in a treestructure. To illustrate, the data file may include informationcorresponding to a system-on-chip (SOC) that includes the multiplecombinatorial gate multiplexers of FIG. 1 or 3 in a tree structure andthat also includes additional electronic circuits and components withinthe SOC.

The GDSII file 826 may be received at a fabrication process 828 tomanufacture the apparatus 100 of FIG. 1, the apparatus 300 of FIG. 3, orany combination thereof, according to transformed information in theGDSII file 826. For example, a device manufacture process may includeproviding the GDSII file 826 to a mask manufacturer 830 to create one ormore masks, such as masks to be used for photolithography processing,illustrated as a representative mask 832. The mask 832 may be usedduring the fabrication process to generate one or more wafers 834, whichmay be tested and separated into dies, such as a representative die 836.The die 836 includes a circuit including the apparatus 100 of FIG. 1,the apparatus 300 of FIG. 3, or any combination thereof. To illustrate,the representative die 836 may include information corresponding to aparallel interface 102 and the multiple combinatorial gate multiplexersof FIG. 1 or 3.

In an illustrative embodiment, the fabrication process 828 includes anapparatus to convert the parallel data input values to serial dataoutput values using combinatorial logic circuits in a tree structurethat may include the parallel interface 102 and the multiplecombinatorial gate multiplexers of FIG. 1 or 3 in a tree structure. Forexample, the fabrication process 828 may include a computer readablestorage medium storing computer executable instructions that areexecutable to cause a serializer, such as the apparatus 100 of FIG. 1,or the apparatus 300 of FIG. 3, to convert the parallel data inputvalues to serial data output values using combinatorial logic circuitsin a tree structure.

The die 836 may be provided to a packaging process 838 where the die 836is incorporated into a representative package 840. For example, thepackage 840 may include the single die 836 or multiple dies, such as asystem-in-package (SiP) arrangement. The package 840 may be configuredto conform to one or more standards or specifications, such as JointElectron Device Engineering Council (JEDEC) standards.

Information regarding the package 840 may be distributed to variousproduct designers, such as via a component library stored at a computer846. The computer 846 may include a processor 848, such as one or moreprocessing cores, coupled to a memory 850. A printed circuit board (PCB)tool may be stored as processor executable instructions at the memory850 to process PCB design information 842 received from a user of thecomputer 846 via a user interface 844. The PCB design information 842may include physical positioning information of a packaged semiconductordevice on a circuit board, the packaged semiconductor devicecorresponding to the package 840 including the apparatus 100 of FIG. 1,the apparatus 300 of FIG. 3, or any combination thereof.

The computer 846 may be configured to transform the PCB designinformation 842 to generate a data file, such as a GERBER file 852 withdata that includes physical positioning information of a packagedsemiconductor device on a circuit board, as well as layout of electricalconnections such as traces and vias, where the packaged semiconductordevice corresponds to the package 840 including the apparatus 100 ofFIG. 1, the apparatus 300 of FIG. 3, or any combination thereof. Inother embodiments, the data file generated by the transformed PCB designinformation may have a format other than a GERBER format.

The GERBER file 852 may be received at a board assembly process 854 andused to create PCBs, such as a representative PCB 856, manufactured inaccordance with the design information stored within the GERBER file852. For example, the GERBER file 852 may be uploaded to one or moremachines for performing various steps of a PCB production process. ThePCB 856 may be populated with electronic components including thepackage 840 to form a represented printed circuit assembly (PCA) 858.

The PCA 858 may be received at a product manufacture process 860 andintegrated into one or more electronic devices, such as a firstrepresentative electronic device 862 and a second representativeelectronic device 864. As an illustrative, non-limiting example, thefirst representative electronic device 862, the second representativeelectronic device 864, or both, may be selected from the group of a settop box, a music player, a video player, an entertainment unit, anavigation device, a communications device, a personal digital assistant(RDA), a fixed location data unit, and a computer. As anotherillustrative, non-limiting example, one or more of the electronicdevices 862 and 864 may be remote units such as mobile phones, hand-heldpersonal communication systems (PCS) units, portable data units such aspersonal data assistants, global positioning system (GPS) enableddevices, navigation devices, fixed location data units such as meterreading equipment, or any other device that stores or retrieves data orcomputer instructions, or any combination thereof. Although one or moreof FIGS. 1-7 may illustrate remote units according to the teachings ofthe disclosure, the disclosure is not limited to these exemplaryillustrated units. Embodiments of the disclosure may be suitablyemployed in any device that includes active integrated circuitry.

Thus, the apparatus 100 of FIG. 1, the apparatus 300 of FIG. 3, or anycombination thereof, may be fabricated, processed, and incorporated intoan electronic device, as described in the illustrative process 800. Oneor more aspects of the embodiments disclosed with respect to FIGS. 1 and3 may be included at various processing stages, such as within thelibrary file 812, the GDSII. file 826, and the GERBER file 852, as wellas stored at the memory 810 of the research computer 806, the memory 818of the design computer 814, the memory 850 of the computer 846, thememory of one or more other computers or processors (not shown) used atthe various stages, such as at the board assembly process 854, and alsoincorporated into one or more other physical embodiments such as themask 832, the die 836, the package 840, the PCA 858, other products suchas prototype circuits or devices (not shown), or any combinationthereof. Although various representative stages of production from aphysical device design to a final product are depicted, in otherembodiments fewer stages may be used or additional stages may beincluded. Similarly, the process 800 may be performed by a singleentity, or by one or more entities performing various stages of theprocess 800.

Those of skill would further appreciate that the various illustrativelogical blocks, configurations, modules, circuits, and algorithm stepsdescribed in connection with the embodiments disclosed herein may beimplemented as electronic hardware, computer software, or combinationsof both. Various illustrative components, blocks, configurations,modules, circuits, and steps have been described above generally interms of their functionality. Whether such functionality is implementedas hardware or software depends upon the particular application anddesign constraints imposed on the overall system. Skilled artisans mayimplement the described functionality in varying ways for eachparticular application, but such implementation decisions should not beinterpreted as causing a departure from the scope of the presentdisclosure.

The steps of a method or algorithm described in connection with theembodiments disclosed herein may be embodied directly in hardware, in asoftware module executed by a processor, or in a combination of the two.A software module may reside in random access memory (RAM), flashmemory, read-only memory (ROM), programmable read-only memory (PROM),erasable programmable read-only memory (EPROM), electrically erasableprogrammable read-only memory (EEPROM), registers, hard disk, aremovable disk, a compact disc read-only memory (CD-ROM), or any otherform of storage medium known in the art. An exemplary storage medium isa non-transitory medium coupled to the processor such that the processorcan read information from, and write information to, the storage medium.In the alternative, the storage medium may be integral to the processor.The processor and the storage medium may reside in anapplication-specific integrated circuit (ASIC). The ASIC may reside in acomputing device or a user terminal. In the alternative, the processorand the storage medium may reside as discrete components in a computingdevice or user terminal.

The previous description of the disclosed embodiments is provided toenable a person skilled in the art to make or use the disclosedembodiments. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the principles defined hereinmay be applied to other embodiments without departing from the scope ofthe disclosure. Thus, the present disclosure is not intended to belimited to the embodiments shown herein but is to be accorded the widestscope possible consistent with the principles and novel features asdefined by the following claims.

What is claimed is:
 1. A method comprising: receiving a first data inputat a combinatorial logic circuit; receiving a second data input at thecombinatorial logic circuit; receiving a first signal at a first controlinput of the combinatorial logic circuit, the first signal formed bycombining a first clock signal having a first phase with a second clocksignal having a second phase; receiving a second signal at a secondcontrol input of the combinatorial logic circuit, the second signalformed by combining a third clock signal having a third phase with afourth clock signal having a fourth phase; and selecting one of thefirst data input and the second data input as a selected output based onthe first signal and the second signal.
 2. The method of claim 1,wherein the combinatorial logic circuit includes at least one NANDmultiplexer.
 3. The method of claim 1, wherein a first duty cyclecorresponding to the first signal is less than a fifty percent dutycycle, wherein a second duty cycle corresponding to the second signal isgreater than the fifty percent duty cycle.
 4. The method of claim 3,wherein the first duty cycle and the second duty cycle arecomplementary.
 5. The method of claim 1, wherein the first, second,third, and fourth clock signals each have a fifty percent duty cycle. 6.The method of claim 1, wherein combining the first clock signal with thesecond clock signal further comprises performing an AND operation on thefirst and second clock signals, wherein combining the third clock signalwith the fourth clock signal further comprises performing an ORoperation on the third and fourth clock signals.
 7. The method of claim1, further comprising: receiving the first and second data inputs from aparallel interface, wherein the selected output provides serial data. 8.The method of claim 1, wherein receiving the first and second datainputs, receiving the first and second signals, and selecting one of thefirst and second data inputs are performed at a serializer integrated ina semiconductor die.
 9. A method comprising: applying a clock signalhaving an uneven duty cycle to a control input of at least one selectionelement of a selection circuit having a tree structure that includesmultiple selection elements, wherein the tree structure includes a datainput tier and a data output tier.
 10. The method of claim 9, whereinthe tree structure is a balanced tree structure that includes a rootselection element having a first input from a first selection element ofa first branch of the tree structure and a second input from a secondselection element of a second branch of the tree structure, wherein thefirst branch and the second branch have an equal number of selectionelements.
 11. The method of claim 9, wherein the tree structure includesan intermediate tier.
 12. The method of claim 9, wherein the data inputtier and the data output tier each include at least one of the multipleselection elements.
 13. The method of claim 9, wherein data inputs froma parallel interface are received at the data input tier, and whereinserial data is output by the data output tier.
 14. The method of claim13, wherein the parallel interface provides seven data inputs, andwherein the duty cycle is about a forty-two percent duty cycle.
 15. Themethod of claim 9, wherein each of the selection elements is alatch-free circuit.
 16. The method of claim 15, wherein the latch-freecircuit includes a plurality of combinatorial logic elements.
 17. Themethod of claim 16, wherein the combinatorial logic elements includeNAND logic elements.
 18. The method of claim 9, wherein the uneven dutycycle corresponds to a number of data inputs.
 19. The method of claim 9,wherein the selection circuit is a serializer integrated in asemiconductor die.
 20. An apparatus comprising: an input set ofselection elements in an input tier of a tree structure; and a selectionelement in an output tier of the tree structure, wherein the input tierincludes inputs to receive input data from a parallel interface, whereinthe output tier includes an output to provide serial output data, andwherein at least one of the selection elements includes a latch-freecircuit that includes NAND logic circuits.
 21. The apparatus of claim20, further comprising: an intermediate set of selection elements in anintermediate tier of the tree structure, wherein the intermediate tieris operative to select between data received from the input tier and toprovide selected data to the output tier.
 22. The apparatus of claim 20integrated in at least one semiconductor die.
 23. The apparatus of claim20, further comprising a device selected from the group consisting of aset top box, a music player, a video player, an entertainment unit, anavigation device, a communications device, a personal digital assistant(PDA), a fixed location data unit, and a computer, into which the treestructure is integrated.
 24. An apparatus comprising: an input set ofselection elements in an input tier of a tree structure; and a selectionelement in an output tier of the tree structure, wherein the output tierincludes a delay element, and wherein the delay element and theselection element include a similar combinatorial logic structure. 25.The apparatus of claim 24, further comprising: an intermediate set ofselection elements in an intermediate tier of e tree structure.
 26. Theapparatus of claim 24 integrated in at least one semiconductor die. 27.The apparatus of claim 24, further comprising a device selected from thegroup consisting of a set top box, a music player, a video player, anentertainment unit, a navigation device, a communications device, apersonal digital assistant (PDA), fixed location data unit, and acomputer, into which the tree structure is integrated.
 28. An apparatuscomprising: means for selecting first data in a first tier of a treestructure; and means for selecting second data in a second tier of thetree structure, wherein the first tier includes inputs to receive thefirst data from a parallel interface, wherein the second tier includesan output to provide serial output data, and wherein at least one of themeans for selecting first data and means for selecting second dataincludes a latch-free circuit that includes NAND logic circuits.
 29. Theapparatus of claim 28 integrated in at least one semiconductor die. 30.The apparatus of claim 28, further comprising a device selected from thegroup consisting of a set top box, a music player, a video player, anentertainment unit, a navigation device, a communications device, apersonal digital assistant (PDA), a fixed location data unit, and acomputer, into which the tree structure is integrated.
 31. A methodcomprising: a first step for receiving a first data input at acombinatorial logic circuit; a second step for receiving a second datainput at the combinatorial logic circuit; a third step for receiving afirst signal at a first control input of the combinatorial logiccircuit, the first signal formed by combining a first clock signalhaving a first phase with a second clock signal having a second phase; afourth step for receiving a second signal at a second control input ofthe combinatorial logic circuit, the second signal formed by combining athird clock signal having a third phase with a fourth clock signalhaving a fourth phase; and a fifth step for selecting one of the firstdata input and the second data input as a selected output based on thefirst multi-phase clock signal and the second multi-phase clock signal.32. The method of claim 31, wherein combining the first clock signalwith the second clock signal further comprises performing an ANDoperation on the first and second clock signals, wherein combining thethird clock signal with the fourth clock signal further comprisesperforming an OR operation on the third and fourth clock signals. 33.The method of claim 31, wherein the first, second, third, fourth, andfifth steps are performed by a serializer integrated into an electronicdevice.
 34. A method comprising: receiving a data file comprising designinformation corresponding to a semiconductor device; and fabricating thesemiconductor device according to the design information, wherein thesemiconductor device comprises: an input set of selection elements in aninput tier of a tree structure; and a selection element in an outputtier of the tree structure, wherein the input tier comprises inputs toreceive input data from a parallel interface, wherein the output tiercomprises an output to provide serial output data, and wherein at leastone of the selection elements comprises a latch-free circuit thatcomprises NAND logic circuits.
 35. The method of claim 34, wherein thedata file has a GDSII format.
 36. The method of claim 34, wherein thedata file has a GERBER format.